Novel process method of source drain spacer engineering to improve transistor capacitance

ABSTRACT

A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.

FIELD OF INVENTION

[0001] The present invention relates generally to semiconductorprocessing, and more particularly to a methodology for source drainspacer engineering to improve transistor capacitance.

BACKGROUND OF THE INVENTION

[0002] Several trends exist presently in the semiconductor andelectronics industry. Devices are continually getting smaller, fasterand requiring less power. A reason for these trends is that morepersonal devices are being fabricated which are relatively small andportable, thereby relying on a battery as its primary supply source. Forexample, cellular phones, personal computing devices, and personal soundsystems are devices which are in great demand in the consumer market. Inaddition to being smaller and more portable, personal devices arerequiring more computational power and speed. In light of all thesetrends, there is an ever increasing demand in the industry for smallerand faster transistors used to provide the core functionality of theintegrated circuits used in these devices.

[0003] Accordingly, in the semiconductor industry there is a continuingtrend toward manufacturing integrated circuits (ICs) with higherdensities. To achieve high densities, there has been and continues to beefforts toward scaling down dimensions (e.g., at submicron levels) onsemiconductor wafers, which are generally produced from bulk silicon. Inorder to accomplish such high densities, smaller feature sizes, smallerseparations between features and more precise feature shapes arerequired in integrated circuits (ICs) fabricated on small rectangularportions of the wafer, commonly known as dies. This may include thewidth and spacing of interconnecting lines, spacing and diameter ofcontact holes, as well as the surface geometry of various other features(e.g., corners and edges). The scaling-down of integrated circuitdimensions can facilitate faster circuit performance and/or switchingspeeds, and can lead to higher effective yield in IC fabrication byproviding more circuits on a die and/or more die per semiconductorwafer.

[0004] The process of manufacturing integrated circuits typicallyconsists of more than a hundred steps, during which hundreds of copiesof an integrated circuit can be formed on a single wafer. This processcan create electrically active regions in and on the semiconductor wafersurface. In MOS transistors, for example, a gate structure is created,which can be energized to establish an electric field within asemiconductor channel, by which current is enabled to flow between asource region and a drain region within the transistor. The source anddrain regions facilitate this conductance by virtue of containing amajority of positively doped (p) or negatively doped (n) materials.

[0005] As device sizes continue to shrink, however, the channel lengthscontinue to be scaled downward, and short channel effects can becomesignificant. For example, hot carrier effects can be experienced inshort channel devices. More particularly, during saturation operation ofa MOS transistor, for example, electrons can gain kinetic energy andbecome “hot”. Some of these hot electrons traveling to the drain can beinjected into a thin gate dielectric proximate the drain junction. Theinjected hot carriers, in turn, often lead to undesired degradation ofthe MOS device operating parameters, such as a shift in thresholdvoltage, changed transconductance, changed drive current/drain currentexchange, device instability, etc.

[0006] Similarly, unwanted source/drain leakage conduction orpunchthrough current can occur as channel lengths shorten. Punchthroughcurrent may be seen as a parasitic current path existing between thedrain and source, which the gate has difficulty in controlling since thecurrent path is located deep in the bulk (substrate) far away from thegate. The actual amount of punchthrough current depends mainly upon thepotential distribution under the channel and on the source/drainjunction depths. As the effective channel length gets shorter, thesource/drain depletion regions get closer together. Punchthroughgenerally occurs when the effective channel length is decreased toroughly the sum of two junction depletion widths.

[0007] In addition, as device densities and operational speeds continueto increase, reduction of the delay times in the MOS devices used inintegrated circuits is desired. These delays are related to the on-stateresistance as well as the junction capacitances of these MOS devices.Working with smaller and more densely packed devices, however, requiresa greater precision in fabrication, which can provide opportunities forerrors to occur. For example, dopant may be unintentionally placed inunwanted areas and may increase junction capacitance and cause bodyleakage, resulting in reduced switching speeds and higher source todrain resistance (Rsd). Imprecisely placed dopants may also migrate intoa channel region, for example, and shorten the channel length adding topossible subsurface leakage current paths.

[0008] Accordingly, improved techniques for fabricating densely packedsemiconductor devices would be desirable. More particularly, it would bedesirable to fabricate semiconductor devices in a manner that mitigatesshort channel effects. Similarly, it would also be desirable to fashionsemiconductor devices such that junction capacitances are reduced andswitching speeds are thereby enhanced.

SUMMARY OF THE INVENTION

[0009] The following presents a simplified summary of the invention inorder to provide a basic understanding of some aspects of the invention.This summary is not an extensive overview of the invention. It isintended neither to identify key or critical elements of the inventionnor to delineate the scope of the invention. Rather, its primary purposeis merely to present one or more concepts of the invention in asimplified form as a prelude to the more detailed description that ispresented later.

[0010] The present invention pertains to formation of a transistor in amanner that mitigates short channel effects and junction capacitances,thereby facilitating enhanced switching speeds. More particularly,compensation regions are formed with dopants implanted relatively deeplyover source and drain regions within a substrate. The compensationregions are spaced apart slightly more than the source and drain regionsto alter potential contours and reduce junction capacitances within thetransistor. The different distances between the source and drain regionsand the compensation regions are achieved by forming and selectivelyadjusting sidewall spacers adjacent to a gate structure of thetransistor. These spacers effectively serve as guides for the dopantsimplanted into the substrate to form the source and drain regions andthe compensation regions.

[0011] According to one aspect of the present invention, a method offorming a transistor is disclosed. The method includes forming a firstoxide layer over a gate structure. The first oxide layer is also formedover portions of a substrate not covered by the gate structure. Theseuncovered portions of the substrate also have source/drain extensionregions and halo regions formed therein. The method further includesforming a nitride layer over the first oxide layer, forming a secondoxide layer over the nitride layer and processing the second oxide layerand nitride layer to form oxide sidewall spacers adjacent the gatestructure. In this manner, the oxide sidewall spacers are situated overa residual portion of nitride material. The method further includesprocessing the oxide sidewall spacers such that they are reduced in sizerelative to the underlying portions of nitride material. Regions of thesubstrate adjacent the gate structure are then doped with a first dopantto form source and drain regions within the substrate. The first dopantis, however, substantially blocked by the oxide sidewall spacers and theunderlying portions of nitride material. Regions of the substrateadjacent the gate structure are then doped again with a second dopant toform first and second compensation regions within the substrate. Thesecond dopant is, however, substantially blocked by the oxide sidewallspacers.

[0012] In accordance with one or more other aspects of the presentinvention, a method of forming a transistor includes forming source anddrain regions within a substrate adjacent to a gate structure formedupon the substrate. The method also includes forming first and secondcompensation regions within the substrate to a depth about twice that ofthe source and drain regions. The source and drain regions and the firstand second compensation regions are separated by a channel regionunderlying the gate structure. The source and drain regions are alsoseparated by a first distance and the first and second compensationregions are separated by a second distance, where the first distance isgreater than the second distance.

[0013] According to one or more other aspects of the present invention,a transistor includes a gate structure formed over a substrate. Thetransistor also includes a source region formed within the substrateadjacent the gate structure and a drain region formed within thesubstrate adjacent the gate structure. A first compensation region isformed within the substrate adjacent the gate structure and within thesource region. Similarly, a second compensation region is formed withinthe substrate adjacent the gate structure and within the drain region.The transistor also has a channel underlying the gate structure andseparating the source and drain regions and the first and secondcompensation regions. The source and drain regions are also separated bya first distance and the first and second compensation regions areseparated by a second distance, where the first distance is greater thanthe second distance.

[0014] To the accomplishment of the foregoing and related ends, thefollowing description and annexed drawings set forth in detail certainillustrative aspects and implementations of the invention. These areindicative of but a few of the various ways in which one or more aspectsof the present invention may be employed. Other aspects, advantages andnovel features of the invention will become apparent from the followingdetailed description of the invention when considered in conjunctionwith the annexed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a simplified, schematic cross-sectional illustration ofa conventional transistor.

[0016]FIG. 2-8 are cross-sectional illustrations depicting aconventional methodology for forming a PMOS transistor, such as thatpresented in FIG. 1.

[0017]FIG. 9 is a flow diagram illustrating an example of a methodologyof forming a transistor in accordance with one or more aspects of thepresent invention.

[0018]FIGS. 10-23 are cross-sectional illustrations of a transistorformed according to one or more aspects of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019] One or more aspects of the present invention are described withreference to the drawings, wherein like reference numerals are generallyutilized to refer to like elements throughout, and wherein the variousstructures are not necessarily drawn to scale. In the followingdescription, for purposes of explanation, numerous specific details areset forth in order to provide a thorough understanding of one or moreaspects of the present invention. It may be evident, however, to oneskilled in the art that one or more aspects of the present invention maybe practiced with a lesser degree of these specific details. In otherinstances, well-known structures and devices are shown in block diagramform in order to facilitate describing one or more aspects of thepresent invention.

[0020] The present invention pertains to formation of a transistor in amanner that mitigates short channel effects and junction capacitances,thereby facilitating enhanced switching speeds. More particularly,compensation regions are formed with dopants implanted relatively deeplyover source and drain regions within a substrate. The compensationregions are spaced apart slightly more than the source and drain regionsto alter potential contours and reduce capacitive contact areas, therebyreducing junction capacitances within the transistor. The differentdistances between the source and drain regions and the compensationregions are achieved by forming and selectively adjusting sidewallspacers adjacent to a gate structure of the transistor. These spacersserve as guides for the dopants implanted into the substrate to form thesource and drain regions and the compensation regions.

[0021] In order to appreciate various aspects of the present invention,a brief description of a conventional MOS device and fabrication processfollows below. FIG. 1 illustrates a conventional semiconductortransistor device 100 that can be fabricated with conventionalcomplimentary MOS (CMOS) processing techniques in a semiconductorsubstrate 102. The device 100 includes a gate structure 104 comprising agate electrode 106 and a gate dielectric 108. The gate electrode 106generally comprises polysilicon or SiGe and overlies the gate dielectric108. Sidewall spacers 110, 112 are located upon either side of the gatestructure 104. As will be discussed further, the sidewall spacers 110,112 impede doping of certain areas or extension regions 114, 116underlying the spacers 110, 112. Two laterally spaced doped source/drainregions 118 and 120 are formed within the substrate 102 and a channelregion 122 is defined therebetween under the gate structure 104.

[0022] In operation, the resistivity of the channel 122 may becontrolled by a voltage applied to the gate electrode 106, wherechanging the gate voltage changes the amount of current flowing throughthe channel 122 between the source and drain. The gate contact orelectrode 106 and the channel 122 are separated by the gate dielectric108, which is an insulator and which opposes current flow between thegate electrode 106 and the channel 122, such that the device does notbecome activated until a sufficient voltage (at least larger than athreshold voltage Vt) is applied to the gate electrode 106.

[0023] To form the device 100, a layer of dielectric material 124 isinitially formed over the substrate 102 (FIG. 2). A gate electrode layer126 (e.g., polysilicon or SiGe) is then formed over the layer ofdielectric material 124 (FIG. 3). The gate electrode layer 126 and thelayer of dielectric material 124 are then patterned (e.g., via etching)to develop the gate structure 104 (FIG. 4). Dopant 128 is then appliedto the gate electrode 106 and to exposed portions of the substrate 102to form extension regions 130, 132 therein (FIG. 5). As will becomeapparent, the extension regions 130, 132 are precursors to portions ofthe source and drain regions 118, 120 formed within the substrate 102.

[0024] A layer of an insulating material 134 (e.g., silicon nitride,silicon oxide) is then formed over the entire structure (FIG. 6). Thelayer of insulating material 134 is selectively removed (e.g., viaanisotropic etching) to form the sidewall spacers 110, 112 on eitherside of the gate structure 104 (FIG. 7). Additional dopant 128 is thenapplied to the gate electrode 106 and the substrate 102, except forthose portions 114, 116 covered by the sidewall spacers 110, 112 (FIG.8). The additional dopant 128 establishes the source and drain regions118, 120 within the substrate 102 on either side of the gate structure104. It will be appreciated that the additional dopant 128 is ofsubstantially the same type as that previously applied in forming theextension regions 130, 132 (e.g., FIG. 5). The channel region 122 isthereby defined within the substrate 102 under the gate structure 104 asthe source and drain regions 118, 120 are formed (FIG. 8).

[0025] Turning now to FIG. 9, a methodology 200 is illustrated forforming a MOS transistor according to one or more aspects of the presentinvention. Although the methodology 200 is illustrated and describedhereinafter as a series of acts or events, it will be appreciated thatthe present invention is not limited by the illustrated ordering of suchacts or events. For example, some acts may occur in different ordersand/or concurrently with other acts or events apart from thoseillustrated and/or described herein. In addition, not all illustratedsteps may be required to implement a methodology in accordance with oneor more aspects of the present invention. Further, one or more of theacts may be carried out in one or more separate acts or phases.

[0026] It will be appreciated that a methodology carried out accordingto one or more aspects of the present invention may be implemented inassociation with the formation and/or processing of structuresillustrated and described herein as well as in association with otherstructures not illustrated or described herein. By way of example, themethod or variants thereof may be used to fabricate a transistor asillustrated and described below with respect to FIGS. 10-23, as well asto devices not shown or described with regard to FIGS. 10-23.

[0027] The methodology 200 begins at 202 wherein a gate structure isformed over a semiconductor substrate. In particular, a layer of gatedielectric material is formed over the semiconductor substrate, a gateelectrode layer is formed over the layer of gate dielectric material,and the gate electrode layer and the layer of gate dielectric materialare patterned to form the gate structure. The gate structure thuscomprises a gate electrode and a gate dielectric. It will be appreciatedthat the layers can be patterned in any suitable manner to form the gatestructure, such as by etching, for example.

[0028] Further, the layer of gate dielectric material and the gateelectrode layer can be applied to the substrate in any number of ways,such as with spin-on techniques, sputtering techniques (e.g., magnetronor ion beam sputtering), growth and/or deposition techniques such aschemical vapor deposition (CVD), for example. The gate dielectricmaterial can be formed to a thickness of about 1 nanometer or more, andcan have an equivalent oxide thickness (EOT) of about 1 nanometer orless, for example, while the gate electrode layer can be formed to athickness of about 50-200 nm, for example.

[0029] Additionally, the substrate generally includes silicon, the gateelectrode layer generally includes doped polysilicon, SiGe or metal, andthe layer of gate dielectric material can comprise a high-k dielectricmaterial, for example. The layer of gate dielectric material mayinclude, for example, any one or more of the following, either alone orin combination: aluminum oxide (Al₂O₃), zirconium silicate, hafniumsilicate, hafnium silicon oxynitride, hafnium oxynitride, zirconiumoxynitride, zirconium silicon oxynitride, hafnium silicon nitride,lanthanum oxide (La₂O₃), hafnium oxide (HfO₂), zirconium oxide (ZrO₂),cerium oxide (CeO₂), bismuth silicon oxide (Bi₄Si₂O₁₂), titanium dioxide(TiO₂), tantalum oxide (Ta₂O₅), tungsten oxide (WO₃), yttrium oxide(Y₂O₃), lanthanum aluminum oxide (LaAlO₃), barium strontium titanate,barium strontium oxide, barium titanate, strontium titanate, PbZrO₃,PST, PZN, PZT and PMN.

[0030] The gate structure may also include a thin oxide over thepolysilicon (e.g., about 1.5 nm thick) and a thin offset spacer (e.g.,deposited and dry etched to a thickness of about 2-20 nm) on thesidewall thereof. Such an initial gate structure and other variationsare contemplated as falling within the scope of the present invention.

[0031] After the gate structure is formed, the methodology proceeds to204 wherein source/drain extension regions are formed. Such extensionregions may, for example, be formed according to HDD (highly dopeddrain) techniques. The extension regions are generally formed within thesubstrate and facilitate absorption of some of the potential associatedwith the drain. In this manner, some of this potential is directed awayfrom the drain/channel interface, thereby mitigating the occurrence ofchannel hot carriers and the adverse effects associated therewith. Byway of example, a p-type dopant having a concentration of about 1 E19 to5E20 atoms/cm³ for a PMOS transistor, or an n-type dopant havingconcentration of about 1 E19 to 9.5E20 atoms/cm³ for an NMOS transistorcan be implanted to a depth of about 100-350 Angstroms, for example. Itwill be appreciated, however, that other implant concentrations andpenetration depths are contemplated as falling within the scope of thepresent invention.

[0032] The methodology then proceeds to 206 wherein halo regions areformed within the semiconductor substrate. Halo implants (or pocketimplants) can facilitate scaling the device channel length by creatinglocalized dopant distributions near the source/drain (S/D) regions,where the distributions may extend, at least partially, under thechannel. In this manner, halos can mitigate unwanted source/drainleakage conduction, or punchthrough current, and as such are sometimesreferred to as “punchthrough stoppers”. A quad high-angle implant may beutilized, for example, to place a halo dose around an edge of the gatestructure in source/drain regions of the semiconductor substrate. In oneexample, such a high-angle implant can place a p-type halo dopant havinga concentration of about 1 to 3E19 atoms/cm³ at the center of the halosfor an NMOS transistor. It will be appreciated, however, that otherimplant concentrations are contemplated as falling within the scope ofthe present invention.

[0033] Then, at 208 a first oxide layer is formed over the gate andexposed portions of the substrate. The first oxide layer can be formedto a thickness of about 20 to 120 Angstroms, for example. A nitridelayer and a second oxide layer are then sequentially formed over thefirst oxide layer at 210 and 212, respectively. The nitride layer can beformed to a thickness of about 50 to 200 Angstroms and the second oxidelayer can be formed to about 400 to 800 Angstroms, for example. It willbe appreciated that the first oxide layer 208, nitride layer 210 andsecond oxide layer 212 can be formed in any number of suitable ways,such as with spin-on techniques, sputtering techniques (e.g., magnetronor ion beam sputtering), growth and/or deposition techniques such aschemical vapor deposition (CVD), for example.

[0034] At 214, the second oxide layer is processed (e.g., via dryetching, ion milling, or other suitable reduction techniques) to revealoxide sidewall spacers adjacent to the gate. Such sidewall spacers canhave a width of about 300 to 800 Angstroms, for example. At 216, some ofthe oxide material is processed to reduce the sidewall spacers and thenitride layer is processed to remove nitride material notcovered/protected by the oxide sidewall spacers. It will be appreciated,however, that the processing of the nitride layer and the oxide sidewallspacers may be performed in separate acts, where nitride material isselectively removed and then oxide is subsequently selectively removed(e.g., via wet etching, CMP, other suitable reduction techniques), wherethe residual nitride material underlying the oxide sidewall spacersserves as a processing stopper. In one example, the second oxide layeron the nitride layer is partially removed, and in another example, theoxide material is completely removed.

[0035] At 218, source and drain implants are performed at relatively lowenergies. These implants are substantially blocked by the sidewallspacers and the residual nitride material as well as any residual secondoxide material that may be residing there-over. Accordingly, thesidewall spacers and residual nitride material together act as aboundary that guides the dopants into source and drain regions of thesubstrate. By way of example, a dopant of Arsenic or other suitablesubstance having a peak concentration of about 0.5 to 5E20 atoms/cm³ maybe implanted at an energy level of about 20 to 50 KeV to provide dopantto an implant range into silicon of about 300-350 Angstroms, forexample.

[0036] A compensation implant is then performed at 220 to place dopantdeeper into the source and drain regions of the substrate. By way ofexample, a dopant of Phosphorous or other suitable substance having apeak concentration of about 5E17 to 5E19 atoms/cm³ may be implanted atan energy level of about 30 to 40 KeV to provide dopant to an implantrange into silicon of about 600-700 Angstroms. It will be appreciatedthat the compensation dopant penetrates deeper into the substrate as aresult of the different (e.g., greater) mass of the compensation dopantrelative to the dopant utilized for the source/drain implants at 218and/or a different (e.g., greater) energy level utilized during thecompensation implant. Regardless, the compensation dopant is generallyimplanted into the substrate to a depth about twice that of thesource/drain implant at 218.

[0037] It will be appreciated that the subsequent selective oxideetching performed at 216 may result in a reduction in the oxide sidewallspacers such that they are not flush with remaining/underlying nitridematerial. In this manner, some of the remaining nitride material mayoverlie underlying substrate areas whereas the oxide spacers no longercover these areas. The type of dopant and/or energy level utilized inthe compensation implant facilitates passage of the compensation dopantthrough the nitride material, whereas the oxide portion of the spacerssubstantially block the compensation dopant (as well as the source/draindopant implanted at 218). Accordingly, a portion of the dopant implantedinto the source and drain regions during the compensation implant at 220is implanted closer to the channel. Moving the deep source/drainjunctions towards the channel in this fashion reduces gate sidewalljunction capacitances by smoothing out the junctions, thus facilitatingimproved switching speeds, as will be further appreciated infra.

[0038] Turning now to FIGS. 10-23, an exemplary technique for forming atransistor according to one or more aspects of the present invention isdisclosed. Initially, a layer of gate dielectric material 302 is formedupon a semiconductor substrate 304 (FIG. 10). It is to be appreciatedthat the term “semiconductor substrate” as used herein can include abase semiconductor wafer (e.g., silicon, SiGe, or an SOI wafer) and anyepitaxial layers or other type semiconductor layers formed thereover orassociated therewith. It is to be further appreciated that elementsdepicted herein are illustrated with particular dimensions relative toone another (e.g., layer to layer dimensions and/or orientations) forpurposes of simplicity and ease of understanding, and that actualdimensions of the elements may differ substantially from thatillustrated herein.

[0039] The layer of gate dielectric material 302 can include any of anumber of suitable materials. Some examples include silicon dioxide,high-k materials, or a stack of such layers. It will be appreciated thatthe layer of gate dielectric material 302 can be formed across thesubstrate 304 in any of a number of suitable manners, including, forexample, sputtering techniques (e.g., magnetron or ion beam sputtering),growth and/or deposition techniques, such as chemical vapor deposition(CVD). The layer of gate dielectric material can also be formed to athickness of about 2.0 nanometers or more to mitigate “tunneling”, andcan have an equivalent oxide thickness (EOT) of about 2.0 nanometers orless, for example, so as to maintain and exhibit desired electricalproperties. A dielectric material having a k of about 7.8 and athickness of about 10 nm, for example, is substantially electricallyequivalent to an oxide gate dielectric having a k of about 3.9 and athickness of about 5 nm.

[0040] A gate electrode layer 306 is then formed over the layer of gatedielectric material 302 (e.g., via spin-on, sputtering, deposition,growth techniques, etc.) (FIG. 11). The gate electrode layer 306generally includes doped polysilicon, SiGe or metal, and can be formedto a thickness of about 200 nanometers or less, for example. The gateelectrode layer 306 ultimately yields a contact area or surface thatprovides a means for applying a voltage to the transistor 300 orotherwise biasing the transistor 300.

[0041] The gate electrode layer 306 and the layer of gate dielectricmaterial 302 are then patterned to form a gate structure 308 (FIG. 12).The gate structure 308 thus comprises a gate electrode 310 and a gatedielectric 312. It will be appreciated that the layers can be patternedin any suitable manner(s), either alone or in combination, to form thegate structure 308, such as by etching.

[0042] After the gate structure 308 is formed, a dopant 314 is appliedto the substrate 304 to form source and drain extension regions 316, 318therein (FIG. 13). Such extension regions may, for example, be formedaccording to HDD (highly doped drain) techniques. The extension regionsabut a channel region 320 within the substrate 304 under the gatestructure 308 and facilitate absorption of some of the potentialassociated with the drain. In this manner, some of this potential isdirected, away from the drain/channel interface, thereby mitigating theoccurrence of channel hot carriers and the adverse effects associatedtherewith. By way of example, a p-type dopant having a concentration ofabout 1 E19 to 5E20 atoms/cm³ for a PMOS transistor, or an n-type dopanthaving concentration of about 1 E19 to 9.5E20 atoms/cm³ for an NMOStransistor can be implanted to a depth of about 300-350 Angstroms, forexample, to establish the extension regions 316, 318. It will beappreciated, however, that other implant concentrations and penetrationdepths are contemplated as falling within the scope of the presentinvention.

[0043] Another dopant 322 is then applied to the substrate 304 to formhalo regions 324, 326 over the extension regions 316, 318 (FIG. 14). Thehalo implants (or pocket implants) can facilitate scaling channel lengthby creating localized dopant distributions near the source/drain (S/D)regions, where the distributions may extend, at least partially, underthe channel. In this manner, halos can mitigate unwanted source/drainleakage conduction, or punchthrough current, and as such, are sometimesreferred to as “punchthrough stoppers”. A quad high-angle implant may beutilized, for example, to place a halo dose around an edge of the gatestructure in source/drain regions of the semiconductor substrate. In oneexample, such a high-angle implant can place a halo dopant having aconcentration of about 1 to 3E19 atoms/cm³ at the center of the halosfor an NMOS transistor. It will be appreciated, however, that otherimplant concentrations are contemplated as falling within the scope ofthe present invention.

[0044] A first oxide layer 328 is then formed over the gate structure308 and exposed portions of the substrate 304 (FIG. 15). The first oxidelayer 328 can be formed to a thickness of about 20 to 120 Angstroms, forexample. A nitride layer 330 is then formed over the first oxide layer328 (FIG. 16), and a second oxide layer 332 is formed over the nitridelayer 330 (FIG. 17). The nitride layer 330 can be formed to a thicknessof about 50 to 200 Angstroms and the second oxide layer 332 can beformed to about 400 to 800 Angstroms, for example. It will beappreciated that the first oxide layer 328, nitride layer 330 and secondoxide layer 332 can be formed in any number of suitable ways, such aswith spin-on techniques, sputtering techniques (e.g., magnetron or ionbeam sputtering), growth and/or deposition techniques such as chemicalvapor deposition (CVD), for example. The layers 328, 330 and 332 are notdrawn to scale in the figures, but instead are shown enlarged to helpfacilitate an understanding of one or more aspects of the presentinvention.

[0045] The second oxide layer 332 is then processed (e.g., via dryetching or other suitable reduction techniques) to reveal oxide sidewallspacers 334, 336 adjacent to the gate structure 308 (FIG. 18). Suchsidewall spacers can have a width 338 of about 300 to 800 Angstroms, forexample. It will be appreciated that this processing is selective suchthat the underlying nitride layer 330 is substantially unaffected by theprocessing.

[0046] The nitride layer 330 is then processed (e.g., etched) to removenitride material not covered/protected by the oxide sidewall spacers334, 336 (FIG. 19). In the example shown the remaining or residualnitride material 330 has an “L” shape. It will be appreciated that thisprocessing is also substantially selective such that the oxide sidewallspacers 334, 336 are not affected thereby. It will be furtherappreciated that any differences in the height and/or other dimension(s)of the oxide spacers 334, 336 depicted in the Figures is merelyincidental and/or the result of intermediate acts that are generallyunderstood, but that are not shown or described herein.

[0047] Alternatively, the “L” shaped region may comprise anothermaterial having a slower etch rate than oxide. For example, the layermay comprise polysilicon or other suitable material, and suchalternatives are contemplated by the present invention. Similarly, thefirst oxide layer could be replaced with another suitable material inaccordance with the present invention.

[0048] A portion of the remaining oxide material is subsequentlyprocessed (e.g., etched) to reduce the size of the sidewall spacers 334,336 and to remove some or all of the exposed portions of the first oxidelayer 328 (FIG. 20). The width 338 (FIGS. 18 and 19) of the sidewallspacers 334, 336 may, for example, be reduced to 338′ (FIG. 20), where338 is greater than 338′. Again, this processing is substantiallyselective such that the remaining (L shaped) nitride material 330 is notaffected thereby. In this manner, portions of the first oxide layer 328underlying the residual nitride material 330 are not affected by theprocessing. Moreover, the underlying L shaped nitride layer 330 canserve as a process (e.g., etch) stopper as the spacers are beingprocessed. It will be appreciated that any differences in the heightand/or other dimension(s) of the residual L shaped nitride material 330depicted in the Figures is merely incidental and/or the result ofintermediate acts that are generally understood, but that are not shownor described herein.

[0049] It will be appreciated that the oxide sidewall spacers 334, 336and the nitride layer 330 are processed such that the sidewall spacers334, 336 are reduced more than the nitride layer 330 (FIG. 20). In thismanner, a portion 339 of the residual L shaped nitride material 330having a width 339′ overlies areas of the substrate 304 that are notcovered by the oxide sidewall spacers 334, 336. This arrangement can beutilized to achieve certain doping profiles in the substrate 304 as willbe described below.

[0050] Additional, dopant 340 is then implanted in forming the sourceand drain regions 342, 344 (FIG. 21). These implants are done atrelatively low energies and are substantially blocked by the sidewallspacers 334, 336 and the residual nitride material 330. Accordingly, thesidewall spacers 334, 336 and residual nitride material 330 together actas a boundary that guides the dopants 340 in forming the source anddrain regions 342, 344 in the substrate 304. By way of example, a dopantof Arsenic or other suitable substance having a concentration of about0.5 to 5E20 atoms/cm³ may be implanted at an energy level of about 20 to50 KeV to provide dopant to an implant range into silicon of about300-350 Angstroms to form the source and drain regions 342, 344. It willbe appreciated, however, that other implant concentrations, energylevels and/or penetration depths are contemplated as falling within thescope of the present invention.

[0051] More dopant 346 is then implanted into the source and drainregions in the substrate 304 to form compensation regions 348, 350 (FIG.22). The dopant 246 in the compensation regions 348, 350 are implantedrelatively deeply into the substrate 304. By way of example, a dopant ofPhosphorous or other suitable substance having a concentration of about5E17 to 5E19 atoms/cm³ may be implanted at an energy level of about 30to 40 KeV to provide dopant to an implant range into silicon of about600-700 Angstroms, for example. It will be appreciated that thecompensation dopant 346 penetrates deeper into the substrate 304 as aresult of the different (e.g., greater) mass and/or energy level of thecompensation dopant 346 relative to the other dopants 314, 322, 340utilized in doping the substrate 304. In general, the compensationdopant 346 is implanted into the substrate 304 to a depth about twicethat of the dopant 340 utilized in establishing the source and drainregions 342, 344.

[0052] It will be appreciated that the selective oxide etching discussedabove with respect to FIG. 20 leaves a portion 339 of the L shapednitride material uncovered by the oxide sidewall spacers 334, 336. Thedopant 346 and/or energy level utilized in the compensation implant(FIG. 22) facilitates passage of the compensation dopant through thenitride material 330, whereas the oxide spacers 334, 336 substantiallyblock the compensation dopant 346, as well as the source/drain dopant340 (FIG. 21). Accordingly, the compensation dopant 346 is implanted inthe substrate closer to the channel 320 than the source/drain dopant340. The separation between the deep compensation implants is thussmaller than it would be had the oxide sidewall spacers not beensubsequently selectively processed (e.g., etched) to remove some of theoxide material and expose a portion 339 of the L shaped nitride layer.This is evident by a comparison of the distance 352 between the deepcompensation implants 348, 350 where the sidewall spacers 334, 336 havebeen processed further (FIG. 22) and the distance 352′ between the deepcompensation implants 348, 350 in a situation where the sidewall spacers334, 336 have not been subsequently processed (FIG. 23).

[0053] It can be seen in FIGS. 22 and 23 that 352′ is greater than 352by an amount equal to two times the width 339′ of the portion 339 of theL shaped nitride layer 330 that is not covered by the oxide spacers 334,336. Since the source/drain regions 342, 344 and the compensationregions 348, 350 are somewhat aligned FIG. 23, the distance 352′ canalso be said to correspond to the distance between the source 342 anddrain 344 regions. Moving the deep junctions towards the channel 320 inthe manner illustrated in FIG. 22 reduces junction areas wherecapacitance can arise. Reducing bottom wall areas in this fashionmitigates the opportunity for capacitive build up to occur, and therebyfacilitates improved switching speeds.

[0054] Accordingly, it will be appreciated that one or more aspects ofthe present invention facilitate channel length scaling by alteringshort channel characteristics. By changing the doping profile in andaround the channel region, the distribution of the dopants and potentialcontours can be changed to facilitate attaining higher switching speedsin a MOS transistor, at a higher drive current (Ids), but at a lowerjunction capacitance under the gate (Cjswg).

[0055] Although the invention has been shown and described with respectto one or more implementations, equivalent alterations and modificationswill occur to others skilled in the art based upon a reading andunderstanding of this specification and the annexed drawings. Theinvention includes all such modifications and alterations and is limitedonly by the scope of the following claims. In particular regard to thevarious functions performed by the above described components(assemblies, devices, circuits, etc.), the terms (including a referenceto a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component which performsthe specified function of the described component (i.e., that isfunctionally equivalent), even though not structurally equivalent to thedisclosed structure which performs the function in the hereinillustrated exemplary implementations of the invention. In addition,while a particular feature of the invention may have been disclosed withrespect to only one of several implementations, such feature may becombined with one or more other features of the other implementations asmay be desired and advantageous for any given or particular application.Furthermore, to the extent that the terms “includes”, “having”, “has”,“with”, or variants thereof are used in either the detailed descriptionor the claims, such terms are intended to be inclusive in a mannersimilar to the term “comprising.”

What is claimed is:
 1. A method of forming a transistor comprising:forming a first oxide layer over a gate structure and portions of asubstrate not covered by the gate structure, where portions of thesubstrate not covered by the gate structure have source/drain extensionregions and halo regions formed therein; forming a nitride layer overthe first oxide layer; forming a second oxide layer over the nitridelayer; processing the second oxide layer and nitride layer to form oxidesidewall spacers having a portion of nitride material there-underadjacent the gate structure; processing the oxide sidewall spacers suchthat they are reduced in size relative to the underlying portions ofnitride material; doping regions of the substrate adjacent the gatestructure with a first dopant to form source and drain regions withinthe substrate, the first dopant being substantially blocked by the oxidesidewall spacers and the underlying portions of nitride material; anddoping regions of the substrate adjacent the gate structure with asecond dopant to form first and second compensation regions within thesubstrate, the second dopant being substantially blocked by the oxidesidewall spacers.
 2. The method of claim 1, wherein the source and drainregions are separated by a first distance, the first and secondcompensation regions are separated by a second distance and the firstdistance is greater than the second distance.
 3. The method of claim 1,wherein the oxide sidewall spacers are processed according to at leastone of wet etching and dry etching.
 4. The method of claim 3, whereinthe underlying portions of nitride material serve as etch stoppers asthe oxide sidewall spacers are processed.
 5. The method of claim 1,wherein the second oxide layer and nitride layer are processed viaetching.
 6. The method of claim 1, wherein extension regions are formedwith a p-type dopant having a concentration of about 1E19 to 5E20atoms/cm³ for a PMOS transistor, or an n-type dopant havingconcentration of about 1E19 to 9.5E20 atoms/cm³ for an NMOS transistorhaving a final junction depth of about 100-350 Angstroms within thesubstrate.
 7. The method of claim 1, wherein the halo regions are formedwith a p-type dopant having a peak concentration of about 1 to 3E19atoms/cm³ for an NMOS transistor.
 8. The method of claim 1, wherein thefirst oxide layer is formed to a thickness of about 60 to 120 Angstroms.9. The method of claim 1, wherein the nitride layer is formed to athickness of about 50 to 200 Angstroms.
 10. The method of claim 1,wherein the second oxide layer is formed to a thickness of about 300 to800 Angstroms.
 11. The method of claim 1, wherein at least one of thefirst oxide layer, nitride layer and second oxide layer are formedaccording to at least one of spin-on techniques, sputtering techniques,growth techniques and deposition techniques.
 12. The method of claim 1,wherein the source and drain regions are formed with a dopant ofArsenic.
 13. The method of claim 12, wherein the source and drainregions are formed with a dopant having a concentration of about 5E19 to5E20 atoms/cm³.
 14. The method of claim 13, wherein the source and drainregions are formed with a dopant implanted at an energy level of about20 to 50 KeV.
 15. The method of claim 14, wherein the source and drainregions are formed with a doping profile peak to a depth of about300-350 Angstroms.
 16. The method of claim 12, wherein the compensationregions are formed with a dopant of Phosphorous.
 17. The method of claim16, wherein the compensation regions are formed with a dopant having aconcentration of about 5E17 to 5E19 atoms/cm³.
 18. The method of claim17, wherein the compensation regions are formed with a dopant implantedat an energy level of about 30 to 40 KeV.
 19. The method of claim 18,wherein the compensation regions are formed with a doping profile peakto a depth of about 600-700 Angstroms.
 20. The method of claim 1,wherein the compensation regions extend inwardly toward a channel regionunderlying the gate structure an amount greater than that of the sourceand drain regions.
 21. The method of claim 1, wherein the portions ofnitride material underlying the oxide sidewall spacers are L shaped. 22.A method of forming a transistor comprising: forming source and drainregions within a substrate adjacent to a gate structure formed upon thesubstrate; and forming first and second compensation regions within thesubstrate, the source and drain regions and the first and secondcompensation regions being separated by a channel region underlying thegate structure, the source and drain regions being further separated bya first distance and the first and second compensation regions beingseparated by a second distance, the first distance being greater thanthe second distance.
 23. The method of claim 22, wherein the source anddrain regions are formed with a dopant of Arsenic having a concentrationof about 5E19 to 5E20 atoms/cm³ implanted at an energy level of about 20to 50 KeV to a depth of about 300-350 Angstroms.
 24. The method of claim23, wherein the compensation regions are formed with a dopant ofPhosphorous having a concentration of about 5E17 to 5E19 atoms/cm³implanted at an energy level of about 30 to 40 KeV to a depth of about600-700 Angstroms.
 25. The method of claim 22, wherein forming thesource and drain regions and the first and second compensation regioncomprises: forming sidewall spacers on lateral edges of the gatestructure; altering a structure of the sidewall spacers; doping thesubstrate region with a source/drain implant, wherein a dopant type or adopant energy associated therewith is such that the altered sidewallspacer structure blocks the source/drain implant in a substrate regionthereunder; and doping the substrate region with a compensation implant,wherein a dopant type or a dopant energy associated therewith is suchthat the altered sidewall spacer structure only partially blocks thecompensation implant in the substrate region thereunder, therebyresulting in compensation regions extending toward a channel regionwithin the substrate from the source and drain regions, respectively.26. The method of claim 25, wherein forming sidewall spacers comprises:forming a first oxide layer over the gate structure; forming a nitridelayer over the first oxide layer; forming a second oxide layer over thefirst oxide layer; and etching the second oxide layer and nitride layerin a generally anisotropic manner.
 27. The method of claim 26, whereinaltering the structure of the sidewall spacer comprises etching thesecond oxide layer, thereby reducing a size thereof.
 28. A transistorcomprising: a gate structure formed over a substrate; a source regionformed within the substrate adjacent the gate structure; a drain regionformed within the substrate adjacent the gate structure; a firstcompensation region formed within the substrate adjacent the gatestructure and within the source region; a second compensation regionformed within the substrate adjacent the gate structure and within thedrain region; a channel underlying the gate structure and separating thesource and drain regions and the first and second compensation regions,the source and drain regions being separated by a first distance and thefirst and second compensation regions being separated by a seconddistance, the first distance being greater than the second distance. 29.A method of forming a transistor, comprising: forming a first spacermaterial layer over a gate structure and portions of a semiconductorbody not covered by the gate structure, wherein portions of thesemiconductor body not covered by the gate structure have source/drainextension regions and halo regions formed therein; forming a secondspacer material layer over the first spacer material layer; forming athird spacer material layer over the second spacer material layer;processing the second and third spacer material layers to form sidewallspacers substantially adjacent the gate structure, and each having an“L” shaped portion of the second spacer material with the third spacermaterial residing thereover; processing the third spacer materialoverlying the “L” shaped second spacer material portions such that thethird spacer material is reduced in size relative to the underlyingportions of the second spacer material and exposing a portion of the “L”shaped second spacer material; doping regions of the semiconductor bodyadjacent the gate structure with a first dopant to form source and drainregions within the substrate, the first dopant being substantiallyblocked by the “L” shaped second spacer material; and doping regions ofthe semiconductor body adjacent the gate structure with a second dopantto form first and second compensation regions within the substrate, thesecond dopant being substantially blocked by the third spacer material,but not by the exposed portion of the “L” shaped second spacer material.30. The method of claim 29, wherein the second spacer material comprisespolysilicon and the third spacer comprises oxide.
 31. The method ofclaim 30, wherein processing the second and third spacer material layerscomprises etching, and wherein the oxide etches at a substantiallyfaster rate than the polysilicon.
 32. The method of claim 29, whereinthe gate structure comprises a gate electrode material overlying a gatedielectric, wherein the gate electrode material has sidewalls associatedtherewith, and wherein offset spacer material resides on the sidewalls.33. The method of claim 32, wherein the gate electrode materialcomprises polysilicon, silicon germanium or a metal.
 34. A transistor,comprising: a gate structure overlying a semiconductor body; source anddrain regions having a first depth and a first conductivity type withinthe semiconductor body, and defining a channel region therebetweenhaving a second conductivity type below the gate structure; extensionregions of the first conductivity type having a second depth within thesemiconductor body, and disposed between the source and drain regionsand the channel, respectively; halo regions of the second conductivitytype having a third depth within the semiconductor body, and extendingbelow the extension regions, wherein the third depth is greater than thesecond depth; compensation regions of the first conductivity type havinga portion disposed between the source and drain regions and theircorresponding extension regions with a fourth depth, wherein the fourthdepth is greater than the second depth and less than the third depth,and wherein a dopant concentration of the compensation regions is lessthan a dopant concentration of the source and drain regions, therebydefining a generally laterally extending junction having a first portionnearest the channel corresponding to the extension regions and haloregions, and a second portion corresponding to the compensation regionsand the halo regions, respectively.
 35. The transistor of claim 34,further comprising a multi-component spacer associated with sidewalls ofthe gate structure, the multi-component spacer comprising: an “L” shapedspacer generally adjacent the sidewalls of the gate structure; andanother spacer residing on a first portion of the “L” shaped spacer andexposing a second portion of the “L” shaped spacer, wherein the exposedportion of the “L” shaped spacer has a width that corresponds to a widthof the second portion of the generally laterally extending junction. 36.The transistor of claim 35, wherein the “L” shaped spacer comprises an“L” shaped oxide spacer and an “L” shaped nitride spacer lyingthereover.
 37. The transistor of claim 35, wherein the “L” shaped spacercomprises an “L” shaped oxide spacer and an “L” shaped polysiliconspacer lying thereover, and wherein the another spacer comprises anoxide overlying a portion of the polysilicon.